This page documents the Version 1, Revision 1 (V1R1) electronics design of the hyperspectral imager. If you are working on the firmware or integration of the HSI payload, you should find everything you need here (when it is finished).
NB! If you are going to work with the prototype, please see the "Getting Started" guide at the bottom of this page. Remember that this is a untested prototype and that there are certain precautions you have to take when experimenting with the hardware or firmware. If you have any questions or problems - unplug the camera and reach out to Julian at julian@moon.ai or +47 46 41 66 50.
Introduction
Carrier Board | Carrier Board + Optics | Carrier Board + Optics + FPGA Board |
---|---|---|
Table 1: Renders of V1R1, fall 2017.
PCB - Top View | Assembled PCB - Top View | PCB - Perspective |
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Table 2: Altium Designer Screenshot of production PCB, December 2017
PCB without Components | Assembled PCB | Full camera assembly |
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Table 3:Pictures of production PCB, January 2018
Technical Specifications
Resolution: 2048x1088
Storage: 36GB (4GB eMMC + 32GB microSD)
Memory: 1GB
Processor: Dual Core ARM A9 (Zynq 7030 Series FGPA)
Input Voltage: 4.5-14.5V
Maximum current: 6A
Connectivity: USB 2.0, UART
System Design
Power Supply
To allow for maximum flexibility in development and testing (and unknown satellite provider) the V1R1 is designed for an input voltage of 5-14.5V, at 6A. Supplied with the prototype is a 12V, 5.5A, power supply for desktop use but we can solder on a connector for drone/balloon testing. Any AC/DC power adapter with a 2.1mm/5.5mm barrel jack can be used as long as it is between 5-14.5V and supports currents up to 5A.
The input voltage is connected to a switch-mode power supply module for maximum efficiency and then split into four different power rail for the image sensor and FGPA. The PicoZed board requires 5V, 3.3V and 1.8V and the image sensor 2.0V, 3.0V and 3.3V.
The main SMPS can be controlled through the external connector and shut of power to the entire connector. The four power rails will turn on in sequence after the PicoZed power supplies have turned on using the "Power Good" functionality of the regulators. After all the regulators onboard the PicoZed board are up and running VCCIO_EN pin will go high and turn on the carrier card regulators. Each of the power rails have a designated test point located next to the regulator.
When the camera is powered the green LED labeled "Power" will light up.
List of important parts:
PCBA Designator | Functionality | Part Number | Manufacturer | Operating Temperature | Datasheet |
---|---|---|---|---|---|
U1 | 5V SMPS | LMZ31506 | Texas Instruments | -40 to 85C | http://www.ti.com/lit/ds/symlink/lmz31506.pdf |
U2_A, U2_B | 1500mA LDO | TPS74801 | Texas Instruments | -40 to 125C | http://www.ti.com/lit/ds/symlink/tps74801.pdf |
U3_A, U3_B | 500mA LDO | TPS74701 | Texas Instruments | -40 to 125C | http://www.ti.com/lit/ds/symlink/tps74701.pdf |
FPGA Interface (PicoZed)
Image Sensor
The image sensor used is a CMOSIS CMV2000. The data is read out using low voltage differential singling (LVDS) and controlled using SPI. For maximum quantum efficiency (QA), the variation of the sensor processed on 12um epitaxial (E12) SI wafer is used. The thicker epic-layer increases the sensitivity to light above 600nm significantly. Due to the sensitivity due to high speed data transfer, the data lines are carefully impedance matched following the TIA/EIA 644 standard for LVDS signals.
Clock Generation
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX2-8 | CLK_SRC | Input CLK | Master input clock, frequency range between 5 and 48 MHz |
JX1-17 | OUT_CLK_P | Output CLK | High speed LVDS output clock |
JX1-19 | OUT_CLK_N | Output CLK | High speed LVDS output clock |
JX1-47 | LVDS_CLK_P | Input CLK | High speed LVDS input clock, frequency range between 50 and 480 MHz. Should not be used if PLL is enabled (default). |
JX1-49 | LVDS_CLK_N | Input CLK | High speed LVDS input clock, frequency range between 50 and 480 MHz. Should not be used if PLL is enabled (default). |
Control Pins
The following pins are connected to the Program System (PS) part of the FGPA and are used to control the sensor functionality.
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX2-8 | PS_MIO_9 | OE | Enable the SPI logic level converter* |
JX2-1 | PS_MIO_10 | T_EXP1 | Input to program the exposure time externally. |
JX2-6 | PS_MIO_11 | T_EXP2 | Input to program the exposure time externally in HDR mode. |
JX2-5 | PS_MIO_12 | Frame Request | Frame request pin. When a high level is detected on this pin the programmed number of frames is captured and sent by the sensor. This signal should be at least one period of CLK_IN to assure detection on the rising edge of CLK_IN. |
JX2-2 | PS_MIO_13 | SYS_RES_N | System reset pin, active low signal. Resets the on-board sequencer and must be kept low during start-up. This signal should be at least one period of CLK_IN to assure detection on the rising edge of CLK_IN. |
JX3-41 | PS_MIO_46 | SPI MOSI | Data input pin for the SPI interface. The data to program the image sensor is sent over this pin. |
JX3-40 | PS_MIO_47 | SPI MISO | SPI data output pin |
JX3-42 | PS_MIO_48 | SPI CLOCK | SPI clock. This is the clock on which the SPI runs (max 48Mz) |
JX3-44 | PS_MIO_49 | SPI Enable | SPI enable pin. When this pin is high the data should be written/read on the SPI |
*This pin should have pin pulled high by a resistor so it's not, therefore it's necessary to pull it low immediately after boot.
Data Pins
The following pins are connected to the Program Logic (PL) part of the FGPA and are used to read out data from the sensor.
PicoZed Pin | PicoZed Net Name | Net Name | Comment |
---|---|---|---|
JX1-23 | JX1_LVDS_4_P | CMV_OUT_P9 | LVDS Postitive Data Pin |
JX1-25 | JX1_LVDS_4_N | CMV_OUT_N9 | LVDS Negative Data Pin |
JX1-29 | JX1_LVDS_6_P | CMV_OUT_P12 | LVDS Postitive Data Pin |
JX1-31 | JX1_LVDS_6_N | CMV_OUT_N12 | LVDS Negative Data Pin |
JX1-30 | JX1_LVDS_7_P | CMV_OUT_N8 | LVDS Postitive Data Pin |
JX1-32 | JX1_LVDS_7_N | CMV_OUT_P8 | LVDS Negative Data Pin |
JX1-37 | JX1_LVDS_8_P | CMV_OUT_N14 | LVDS Postitive Data Pin |
JX1-39 | JX1_LVDS_8_N | CMV_OUT_P14 | LVDS Negative Data Pin |
JX1-36 | JX1_LVDS_9_P | CMV_OUT_N6 | LVDS Postitive Data Pin |
JX1-38 | JX1_LVDS_9_N | CMV_OUT_P6 | LVDS Negative Data Pin |
JX1-41 | JX1_LVDS_10_P | CMV_OUT_N15 | LVDS Postitive Data Pin |
JX1-43 | JX1_LVDS_10_N | CMV_OUT_P15 | LVDS Negative Data Pin |
JX1-42 | JX1_LVDS_11_P | CMV_OUT_N4 | LVDS Postitive Data Pin |
JX1-44 | JX1_LVDS_11_N | CMV_OUT_P4 | LVDS Negative Data Pin |
JX1-48 | JX1_LVDS_13_P | CMV_OUT_N3 | LVDS Postitive Data Pin |
JX1-50 | JX1_LVDS_13_N | CMV_OUT_P3 | LVDS Negative Data Pin |
JX1-54 | JX1_LVDS_15_P | CMV_OUT_N0 | OUTCTR_N |
JX1-56 | JX1_LVDS_15_N | CMV_OUT_P0 | OUTCTR_P |
JX1-61 | JX1_LVDS_16_P | CMV_OUT_N16 | LVDS Postitive Data Pin |
JX1-63 | JX1_LVDS_16_N | CMV_OUT_P16 | LVDS Negative Data Pin |
JX1-62 | JX1_LVDS_17_P | CMV_OUT_N1 | LVDS Postitive Data Pin |
JX1-64 | JX1_LVDS_17_N | CMV_OUT_P1 | LVDS Negative Data Pin |
JX1-67 | JX1_LVDS_18_P | CMV_OUT_N13 | LVDS Postitive Data Pin |
JX1-69 | JX1_LVDS_18_N | CMV_OUT_P13 | LVDS Negative Data Pin |
JX1-68 | JX1_LVDS_19_P | CMV_OUT_N7 | LVDS Postitive Data Pin |
JX1-70 | JX1_LVDS_19_N | CMV_OUT_P7 | LVDS Negative Data Pin |
JX1-73 | JX1_LVDS_20_P | CMV_OUT_N11 | LVDS Postitive Data Pin |
JX1-75 | JX1_LVDS_20_N | CMV_OUT_P11 | LVDS Negative Data Pin |
JX1-74 | JX1_LVDS_21_P | CMV_OUT_N5 | LVDS Postitive Data Pin |
JX1-76 | JX1_LVDS_21_N | CMV_OUT_P5 | LVDS Negative Data Pin |
JX1-81 | JX1_LVDS_22_P | CMV_OUT_N10 | LVDS Postitive Data Pin |
JX1-83 | JX1_LVDS_22_N | CMV_OUT_P10 | LVDS Negative Data Pin |
JX1-82 | JX1_LVDS_23_P | CMV_OUT_N2 | LVDS Postitive Data Pin |
JX1-84 | JX1_LVDS_23_N | CMV_OUT_P2 | LVDS Negative Data Pin |
Quantum Efficiency
USB 2.0 Connection
The USB port labeled "DATA" is the USB 2.0 line and it is used to stream the picture. The imager uses USB-C ports because they can support USB 3.1, with a high enough data rate to stream the image. USB-C can also (in future prototypes) be used to power the entire design, but for now they are implemented as USB 2.0 ports.
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX3-67 | USB_OTG_P | Data+ | Postive USB data pin |
JX3-69 | USB_OTG_N | Data- | Negative USB Data pin |
USB-UART Connection
USB connection for debugging. It is connected to UART through a FTDI USB-UART bridge that provides USB driver firmware, meaning there's no need to install a driver and it can be read/written using a regular terminal with baud rates up to 3 million symbols per second. A TX and RX indicator is provided on the pcb for debug, to indicate if the camera is receiving or sending data over UART.
Because of limited MIO pins available the USB-UART is shared with the bus connector UART. A 2-channel single-pole double throw (SPDT) bidirectional switch is used to switch between the two connectors. By default it's routed to the USB-UART but by setting pin PS_MIO_51 high the data is routed to pin 3 and 4 on the bus connector.
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX2-3 | PS_MIO_14 | TX | |
JX2-4 | PS_MIO_15 | RX | |
JX3-64 | PS_MIO_51 | SPDT Switch | Set to '0' for USB and '1' for bus connector |
SD Card Interface
The payload supports microSD cards for up to 32GB of storage. Because SDIO is considered a high-speed signal it is routed on the bottom layer of the PCB and all the clock and data traces are length matched to xx mm.
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX3-43 | PS_MIO_40 | Clock | |
JX3-34 | PS_MIO_41 | Commands | |
JX3-37 | PS_MIO_42 | Data0 | |
JX3-36 | PS_MIO_43 | Data1 | |
JX3-39 | PS_MIO_44 | Data2 | |
JX3-48 | PS_MIO_45 | Data3 | |
JX3-66 | PS_MIO_50 | CD |
JTAG Connector
There's a 14-pin JTAG Xilinx connector on the board for programming the two ARM cores and FPGA. In addition to the JTAG lines, there's a 3V3 reference voltage and GND pin.
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX1-1 | JTAG_TCK | ||
JX1-2 | JTAG_TMS | ||
JX1-3 | JTAG_TDO | ||
JX1-4 | JTAG_TDI | ||
JX1-6 | CARRIER_RST |
LED Indicators
In addition to the green power LED on the PicoZed board, there are four orange LEDs on the carrier board with the following functionality:
Indicator | Label | Functionality |
---|---|---|
LED1 | Power | Indicates if the payload has power |
LED2 | TX | Indicates if the payload is transmitting on debug |
LED3 | RX | Indicates if the payload is receiving on debug |
LED4 | FPGA | Indicates if the Program Logic (PL) is ready to go |
Board Outline and Material
External Connector (Bus Connector)
Connector Number | PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|---|
1 | - | - | 3.3V Supply | Can power small peripherals or be used as reference voltage |
2 | JX2-11 | PG_CARRIER | ||
3 | JX2-4 | UART RX | ||
4 | JX2-3 | UART TX | ||
5 | JX1-6 | CARRIER_RST | ||
6 | JX1-5 | PWR_ENABLE | ||
7 | JX2-10 | VCCIO_EN | ||
8 | - | - | Ground pin |
Production Design Files
Type | File | Kind | Comment |
---|---|---|---|
Schematic | Missing watermark, not made pretty yet, duplicate components and some of the component values are wrong. | ||
Bill-of-materials | Bill of materials with pricing information. | ||
Gerber | ntnu-hsi-prototype-SlotHoles.TXT | NC Drill Top Solder Top Paste Top Overlay Top Signal Top Pad Bottom Pad Middle Signal Middle Signal Board Outline Gerber drill Bottom Solder Bottom Paste Bottom Overlay Bottom Signal | Gerber files sent to production, not that slots are in a separate drill file. |
Altium Designer | Altium Designer 17 project files |
Datasheets
Part | Link to datasheet |
---|---|
CMV2000 | |
LMZ31506 | |
How-To Guide
NB! The power supply is limited to 5.5A, make sure the code you are running won't draw that much power! (This is common in FPGA payloads, at full speed they can draw much more current than the satellite can handle).
Proper mode of operation:
1) Power on, with the PicoZed board in (should never be removed).
2) Set the OE pin LOW to enable the SPI logic level converter for the image sensor.
3) Set the UART selector LOW to route the signal through the debug USB connector.