This page documents the Version 1, Revision 1 (V1R1) electronics design of the hyperspectral imager. If you are working on the firmware or integration of the HSI payload, you should find everything you need here (when it is finished).
Introduction
Carrier Board | Carrier Board + Optics | Carrier Board + Optics + FPGA Board |
---|---|---|
Table 1: Renders of V1R1, fall 2017.
PCB - Top View | Assembled PCB - Top View | PCB - Perspective |
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Table 2: Altium Designer Screenshot of production PCB, December 2017
PCB without Components | PCB with components | Full camera assembly |
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Table 3:Pictures of production PCB, January 2018
Technical Specifications
Resolution: 2048x1088
Storage: 36GB (4GB eMMC + 32GB microSD)
Memory: 1GB
Processor: Dual Core ARM A9 (Zynq 7030 Series FGPA)
Input Voltage: 4.5-14.5V
Maximum current: 6A
USB 2.0
System Design
Power Supply
To allow for maximum flexibility in development and testing (and unknown satellite provider) the V1R1 is designed for an input voltage of 5-18V, at 6A. Supplied with the prototype is a 12V, 5A, power supply for desktop use but we can solder on a connector for drone/balloon testing. Any AC/DC power adapter with a 2.1mm/5.5mm barrel jack can be used as long as it is between 5-14.5V and supports currents up to 5A.
The input voltage is connected to a switch-mode power supply module for maximum efficiency and then split into four different power rail for the image sensor and FGPA. The PicoZed board requires 5V, 3.3V and 1.8V and the image sensor 2.0V, 3.0V and 3.3V.
The main SMPS can be controlled through the external connector and shut of power to the entire connector. The four power rails will turn on in sequence after the PicoZed power supplies have turned on using the "Power Good" functionality of the regulators. After all the regulators onboard the PicoZed board are up and running VCCIO_EN pin will go high and turn on the carrier card regulators. Each of the power rails have a designated test point located next to the regulator.
When the camera is powered the green LED labeled "Power" will light up.
List of important parts:
PCBA Designator | Functionality | Part Number | Manufacturer | Specification | Datasheet |
---|---|---|---|---|---|
U1 | 5V SMPS | LMZ31506 | Texas Instruments | ||
U2 | 1500mA LDO | TPS74801 | Texas Instruments | ||
U3 | 500mA LDO | TPS74701 | Texas Instruments |
Image Sensor
The image sensor used is a CMOSIS CMV2000. The data is read out using low voltage differential singling (LVDS) and controlled using SPI. For maximum quantum efficiency (QA), the variation of the sensor processed on 12um epitaxial (E12) SI wafer is used. The thicker epic-layer increases the sensitivity to light above 600nm significantly. Due to the sensitivity due to high speed data transfer, the data lines are carefully impedance matched following the TIA/EIA 644 standard for LVDS signals.
Clock Generation
Control Pins
The following pins are connected to the Program System (PS) part of the FGPA and are used to control the sensor functionality.
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX2-8 | PS_MIO_9 | OE | |
JX2-1 | PS_MIO_10 | T_EXP1 | |
JX2-6 | PS_MIO_11 | T_EXP2 | |
JX2-5 | PS_MIO_12 | Frame Request | |
JX2-2 | PS_MIO_13 | SYS_RES_N | |
JX3-41 | PS_MIO_46 | SPI Mosi | |
JX3-40 | PS_MIO_47 | SPI Miso | |
JX3-42 | PS_MIO_48 | SPI Clock | |
JX3-44 | PS_MIO_49 | SPI Enable |
Data Pins
The following pins are connected to the Program Logic (PL) part of the FGPA and are used to read out data from the sensor.
PicoZed Pin | Net Name | Comment |
---|---|---|
JX1_LVDS_2_P | CMV_OUT_P | |
JX1_LVDS_2_N |
| |
JX1_LVDS_4_P | ||
JX1_LVDS_4_N | ||
JX1_LVDS_6_P | ||
JX1_LVDS_6_N | ||
JX1_LVDS_7_P | ||
JX1_LVDS_7_N | ||
JX1_LVDS_8_P | ||
JX1_LVDS_8_N | ||
JX1_LVDS_9_P | ||
JX1_LVDS_9_N | ||
JX1_LVDS_10_P | ||
JX1_LVDS_10_N | ||
JX1_LVDS_11_P | ||
JX1_LVDS_11_N | ||
JX1_LVDS_12_P | ||
JX1_LVDS_12_N | ||
JX1_LVDS_13_P | ||
JX1_LVDS_13_N | ||
JX1_LVDS_14_P | ||
JX1_LVDS_14_N | ||
JX1_LVDS_15_P | ||
JX1_LVDS_15_N | ||
JX1_LVDS_16_P | ||
JX1_LVDS_16_N | ||
JX1_LVDS_17_P | ||
JX1_LVDS_17_N | ||
JX1_LVDS_18_P | ||
JX1_LVDS_18_N | ||
JX1_LVDS_19_P | ||
JX1_LVDS_19_N | ||
JX1_LVDS_20_P | ||
JX1_LVDS_20_N | ||
JX1_LVDS_21_P | ||
JX1_LVDS_21_N | ||
JX1_LVDS_22_P | ||
JX1_LVDS_22_N | ||
JX1_LVDS_23_P | ||
JX1_LVDS_23_N |
FPGA Interface (PicoZed)
SD Card Interface
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX3-43 | PS_MIO_40 | Clock | |
JX3-34 | PS_MIO_41 | Commands | |
JX3-37 | PS_MIO_42 | Data0 | |
JX3-36 | PS_MIO_43 | Data1 | |
JX3-39 | PS_MIO_44 | Data2 | |
JX3-48 | PS_MIO_45 | Data3 | |
JX3-66 | PS_MIO_50 | CD |
USB-UART Connection
USB connection for debugging. It is connected to UART through a FTDI USB-UART bridge that provides USB driver firmware, meaning there's no need to install a driver and it can be read/written using a regular terminal with baud rates up to 3 million symbols per second. A TX and RX indicator is provided on the pcb for debug, to indicate if the camera is receiving or sending data over UART.
Because of limited MIO pins available the USB-UART is shared with the bus connector UART. A 2-channel single-pole double throw (SPDT) bidirectional switch is used to switch between the two connectors. By default it's routed to the USB-UART but by setting pin PS_MIO_51 high the data is routed to pin 3 and 4 on the bus connector.
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX2-3 | PS_MIO_14 | TX | |
JX2-4 | PS_MIO_15 | RX | |
JX3-64 | PS_MIO_51 | SPDT Switch | Set to '0' for USB and '1' for bus connector |
USB 2.0 Connection
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX3-67 | USB_OTG_P | Data+ | |
JX3-69 | USB_OTG_N | Data- |
External Connector (Bus Connector)
Connector Number | PicoZed Pin | Functionality | Comment | |
---|---|---|---|---|
1 | - | 3.3V Supply | Can power small peripherals or be used as reference voltage | |
2 | PG_CARRIER | |||
3 | UART RX | |||
4 | UART TX | |||
5 | JX1-6 | CARRIER_RST | ||
6 | PWR_ENABLE | |||
7 | JX2-10 | VCCIO_EN | ||
8 | - | Ground pin |
JTAG Connector
PicoZed Pin | Net Name | Functionality | Comment |
---|---|---|---|
JX1-1 | JTAG_TCK | ||
JX1-2 | JTAG_TMS | ||
JX1-3 | JTAG_TDO | ||
JX1-4 | JTAG_TDI | ||
JX1-6 | CARRIER_RST |
LED Indicators
Board Outline and Material
Production Design Files
Type | File | Kind | Comment |
---|---|---|---|
Schematic | Missing watermark, not made pretty yet, duplicate components and some of the component values are wrong. | ||
Gerber | ntnu-hsi-prototype-SlotHoles.TXT | NC Drill Top Solder Top Paste Top Overlay Top Signal Top Pad Bottom Pad Middle Signal Middle Signal Board Outline Gerber drill Bottom Solder Bottom Paste Bottom Overlay Bottom Signal | Gerber files sent to production, not that slots are in a separate drill file. |
Altium Designer | Altium Designer 17 project files | ||
Bill-of-materials |
Datasheets
Part | Link to datasheet |
---|---|
CMV2000 | |