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TDT01 is a specialization course focusing on specialist topics within computer architecture. This year's version will cover 1) dynamic binary translation/optimization and 2) big landmark ideas in computer architecture.
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Course responsible: Rakesh Kumar
Students 2018
Morten Johannes Barbala
Mathias Havdal
Jon Andreas Melbye
Janusa Ragunathan
Even Olsson Rogstadkjærnet
Eggan, Alf Martin Holberg
Gowayed, Yara Mohsen Mohamed Abdalhamid
Gundersen, Martin
Jordet, Ludvig Samuelsen
Kaldager, Andreas Kolstø
Monsen, Kristoffer Venæs
Pedersen, Ole Kristian Eidem
Roland, Katrine
Soliman, Taha Ibrahim Ibrahim
Vedvik, Edgar Mo
Ås, Fredrik
Seim Karstang, Vegard Jørgen Valstad
If you are not on this list, but intend to follow TDT01 you need to contact Rakesh ASAP.
Meetings (Date, time, and venue to be decided)
05/09-16 1100-1200 (ITV-242)Meeting 1: Startup meeting
05/10-16 1300-1500 (ITV-242): Discussion 1
26/10-16 1300-1500 (ITV-242): Discussion 2
- 21 Sept, 12:00-13:00 (Room 242 IT-bygget)
Meeting 2: Discussion 1 - 17 Oct, 12:00-14:00 (Room 454 IT-bygget)
Meeting 3: Discussion 2 - 31 Oct, 13:00-15:00 (Room Realfagbygget: R Botanikk 2 (360.D1-161))
Meeting 4: Discussion 3 - 8 Nov, 12:00-14:00 (Room 122 IT-bygget) 09/11-16 1300-1500 (ITV-242): Discussion 3
Reading list
Note: To access the full versions of the papers from IEEE and ACM you need to have an NTNU IP address. If you are not on campus, try VPN or a terminal server.
Energy
Efficient ComputingDynamic binary translation/optimization:
1. IA-32 processor with a wide-voltage-operating range in 32-nm CMOS (Jon Andreas Melbye) The Transmeta Code Morphing Software: using speculation, recovery, and adaptive retranslation to address real-life challenges (Gowayed, Yara Mohsen Mohamed Abdalhamid) [Slides]
2. Low overhead dynamic binary translation on ARM (Eggan, Alf Martin Holberg 2. Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance (Morten Johannes Barbala)
3. Criticality Stacks: Identifying Critical Threads in Parallel Programs using Synchronization Behavior (Even Olsson Rogstadkjærne) Dynamo: a transparent dynamic optimization system (Ås, Fredrik)[Slides]
4. GRAPE: Minimizing Energy for GPU Applications with Performance Requirements (Mathias Havdal) rePLay: A Hardware Framework for Dynamic Optimization (Jordet, Ludvig Samuelsen)
Landmark ideas in computer architecture
5. Software and the Concurrency Revolution (Seim Karstang, Vegard)[Slides]
6. Dark Silicon and the End of Multicore Scaling (Roland, Katrine)
7. 5. Conservation Cores: Reducing the Energy of Mature Computation (Janusa RagunathanComputations (Monsen, Kristoffer Venæs)
68. Neural Acceleration for General-Purpose Approximate Programs (Jørgen Valstad) Amdahl’s Law for Tail Latency (Gundersen, Martin)
9. The future of microprocessors (Vedvik, Edgar Mo)
10. Challenges in computer architecture evaluation (Soliman, Taha Ibrahim Ibrahim)
11. The load slice core microarchitecture (Pedersen, Ole Kristian Eidem)
12. Needle : Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs (Kaldager, Andreas Kolstø)[Slides]