Register map:
Field | Description | Unit | Bits |
---|---|---|---|
Control register (0x00) | |||
Start | Core starts transfer when this bit is set to 1 | 0 | |
Error IRQ enable | Trigger IRQ when error condition arises | 4 | |
Completion IRQ enable | Trigger IRQ when transfer is complete | 5 | |
Length | Length of transfer | c | 31-12 |
Status register (0x04) | |||
Transfer done | Indicates that transfer has completed | 0 | |
Error code | Indicates error condition that occured during transfer | 3-1 | |
Error IRQ flag | Read: 1 when IRQ triggered due to error Write: Writing 1 clears the IRQ flag | 8 | |
Completion IRQ flag | Read: 1 when IRQ triggered due to completion Write: Writing 1 clears the IRQ flag | 9 | |
Base address register (0x08) | |||
Base address | Address of the first component in the HSI cube | b | 31-0 |
Width register (0x0C) | |||
Width | The width of the HSI cube in number of components, | c | 19-0 |