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TDT01 is a specialization course focusing on specialized topics within computer architecture. This year's edition will focus on 1) Server CPU Microarchitecture, 2) Sustainability and Performance Analysis, and 3) Hardware generation and compilers.

Course responsible: Magnus Själander, Magnus Jahre, and Rakesh Kumar


Students 2024

  Bjerde, Juni Weisteen

  Gabriel, Arran Øystein Kostveit

  Gynnild, Odd Magne Lundereng

  Harmati, Kornel

  Johansen, Markus Bøyum

  Jaatun, Lars Andreassen

  Kuklinski, Patryk

  Larsen, Kristian

  Lundsaunet, Børge

  Løvhaug, Henrik Tøn

  Mack, Stefan

  Ostrzolek, Jakub Jan

  Røgeberg, Eik Hvattum

  Shahzad-Landsverk, Benjamin

  Skaaden, Erlend Paulsen

  Solheim, Jonatan

  Sygard, Magnus Øvre

  Tenstad, Magne Erlendsønn

  Ørn, Filip Kristoff

  Øverås, Hans-Marius


If you are not on this list, but intend to follow TDT01 you need to contact Rakesh ASAP.


Meetings (Date, time, and venue)

    Meeting 1: Startup meeting - Friday, 13th September at 14:00, Realfagbygget R93 (Slides)

    Meeting 2: Discussion 1 -  Friday, 4th October at 14:00, Realfagbygget R93

    Meeting 3: Discussion 2 - Friday, 25th October at 14:00, Realfagbygget R93

    Meeting 4: Discussion 3 - Friday, 15th November at 14:00, Realfagbygget R93


Reading list (preliminary)

 Note: To access the full versions of some of the papers from IEEE and ACM you need to have an NTNU IP address. If you are not on campus, try VPN or a terminal server.


Server CPU Microarchitecture

1. Profiling a warehouse-scale computer 

2. Weeding out Front-End Stalls with Uneven Block Size Instruction Cache 

3. ACIC: Admission-Controlled Instruction Cache


Sustainability and Performance Analysis

4. FOCAL: A First-Order Carbon Model to Assess Processor Sustainability

5. Per-Instruction Cycle Stacks Through Time-Proportional Event Analysis 

6. AIO: An Abstraction for Performance Analysis Across Diverse Accelerator Architectures


Hardware generation and compilers

7. RipTide: A Programmable, Energy-Minimal Dataflow Compiler and Architecture (Recommended for a group with three students)

8. R-HLS: An IR for Dynamic High-Level Synthesis and Memory Disambiguation based on Regions and State Edges 

9. Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations

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