This page describes the Spring 2020 edition of the self-study course in Computer Architecture. The curriculum consists of a predefined set of papers that all students have to read and review. The reviews will be performed individually and submitted through Easy Chair by assigned deadline. After the deadline, the students meet with the course staff to discuss the papers and their reviews with the aim of reaching a consensus regarding the strengths and weaknesses of each paper.
Magnus Jahre and Rakesh Kumar are responsible for this iteration of the course.
List of students
- Joseph
- Fatemeh
- Truls
- Björn
- ???
Schedule
- TBD
Papers
Session 1:
- Barroso, Luiz André, Jeffrey Dean, and Urs Hölzle. "Web search for a planet: The Google cluster architecture." IEEE micro 2 (2003): 22-28.
- Dean, Jeffrey, and Luiz André Barroso. "The tail at scale." Communications of the ACM 56.2 (2013): 74-80.
- Kanev, Svilen, et al. "Profiling a warehouse-scale computer." ISCA'15.
Session 2:
- Barroso, Luiz André, et al. "Attack of the killer microseconds." Commun. ACM 60.4 (2017): 48-54.
- Ferdman, Michael, et al. "Clearing the clouds: a study of emerging scale-out workloads on modern hardware." ASPLOS'12.
- Gan et. al, "An Open-Source Benchmark Suite for Microservices and Their Hardware-Software Implications for Cloud & Edge Systems." ASPLOS'19.
Session 3:
- S. Karandikar et al., “FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud,” in Proceedings of the International Symposium on Computer Architecture (ISCA), 2018, pp. 29–42.
- J. Fowers et al., “A configurable cloud-scale DNN processor for real-time AI,” in Proceedings of the Annual International Symposium on Computer Architecture (ISCA), 2018, pp. 1–14.
- T. Ball and J. R. Larus, “Efficient path profiling,” in Proceedings of the International Symposium on Microarchitecture (MICRO), 1996, pp. 46–57.
Session 4:
- D. Koeplinger, C. Delimitrou, R. Prabhakar, C. Kozyrakis, Y. Zhang, and K. Olukotun, “Automatic Generation of Efficient Accelerators for Reconfigurable Hardware,” in Proceedings of the International Symposium on Computer Architecture (ISCA), 2016, pp. 115–127.
- Q. Huang et al., “Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration,” in Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2019.
- D. Kim, J. Zhao, J. Bachrach, and K. Asanović, “Simmani: Runtime power modeling for arbitrary RTL with automatic signal selection,” in Proceedings of the International Symposium on Microarchitecture (MICRO), 2019, pp. 1050–1062