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| Field | Description | Unit | Bits | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| MM2S (from memory to AXI-Stream) | |||||||||||
| Control register (0x00) | |||||||||||
Start | Core starts transfer when this bit transitions from 0 to 1 | 0 | |||||||||
| Blockwise mode | Cube is read in blocks of specified size | 2 | |||||||||
| Planewise mode | Cube is read planewise, with C_MM2S_NUM_COMP planes in parallel | 3 | |||||||||
| Error IRQ enable | Trigger IRQ when error condition arises | 4 | |||||||||
| Completion IRQ enable | Trigger IRQ when transfer is complete | 5 | |||||||||
| Number of plane transfers | How many plane transfers needed. | 15-8 | |||||||||
| Start offset | Start offset in number of components | c | 23-16 | ||||||||
| Status register (0x04) | |||||||||||
| Transfer done | Indicates that transfer has completed | 0 | |||||||||
| Error code | Indicates error condition(s) that occured during transfer
| 3-1 | |||||||||
| Error IRQ flag | Read: 1 when IRQ triggered due to error | 4 | |||||||||
| Completion IRQ flag | Read: 1 when IRQ triggered due to completion | 5 | |||||||||
| Base address register (0x08) | |||||||||||
| Base address | Address of the first component in the HSI cube | b | 31-0 | ||||||||
| Cube dimension Dimension register 1 (0x0C) | |||||||||||
| Width | The width of the HSI cube | p | 11-0 | ||||||||
| Height | The height of the HSI cube | p | 23-12 | ||||||||
| Depth (low) | Lower 8 bits of the The depth / number of planes of the HSI cube | c | 31-24 | ||||||||
| Block dimension Dimension register 2 (0x10) | |||||||||||
| Block width | log2 of block width in pixels | 3-0 | |||||||||
| Block height | log2 of block height in pixels Constraints: between 1 and 12 | 7-4 | |||||||||
| Depth (high) | High 4 bits of the depth / number of planes of the HSI cube | c | 11-8 | ||||||||
| Last block row size | Size of one row in the last block in each row of blocks | c | 31-12 | ||||||||
| Row size register (0x14) | |||||||||||
| Row size | Number of components in one row of the cube | c | 19-0 | ||||||||
| S2MM (from AXI-Stream to memory) | |||||||||||
| Control register (0x20) | |||||||||||
Start | Core starts transfer when this bit transitions from 0 to 1 | 0 | |||||||||
| Error IRQ enable | Trigger IRQ when error condition arises | 4 | |||||||||
| Completion IRQ enable | Trigger IRQ when transfer is complete | 5 | |||||||||
| Status register (0x24) | |||||||||||
| Transfer done | Indicates that transfer has completed | 0 | |||||||||
| Error code | Indicates error condition that occured during transfer
| 3-1 | |||||||||
| Error IRQ flag | Read: 1 when IRQ triggered due to error | 4 | |||||||||
| Completion IRQ flag | Read: 1 when IRQ triggered due to completion | 5 | Length | The number of bytes received during the transfer | b | 31-6||||||
| Base address register (0x28) | |||||||||||
| Base address | Address of where to store data | b | 31-0 | ||||||||
| Rceived length register (0x2C) | |||||||||||
| Received length | Number of bytes received from start of transfer until TLAST was asserted | b | 31-0 | ||||||||
Units:
c - components
p - pixels
b - bytes