Register map:
| Field | Description | Unit | Bits |
|---|---|---|---|
| MM2S (from memory to AXI-Stream) | |||
| Control register (0x00) | |||
Start | Core starts transfer when this bit is set to 1 | 0 | |
| Error IRQ enable | Trigger IRQ when error condition arises | 4 | |
| Completion IRQ enable | Trigger IRQ when transfer is complete | 5 | |
| Length | Length of transfer | c | 31-12 |
| Status register (0x04) | |||
| Transfer done | Indicates that transfer has completed | 0 | |
| Error code | Indicates error condition that occured during transfer | 3-1 | |
| Error IRQ flag | Read: 1 when IRQ triggered due to error Write: Writing 1 clears the IRQ flag | 8 | |
| Completion IRQ flag | Read: 1 when IRQ triggered due to completion Write: Writing 1 clears the IRQ flag | 9 | |
| Base address register (0x08) | |||
| Base address | Address of the first component in the HSI cube | b | 31-0 |
| Width register (0x0C) | |||
| Width | The width of the HSI cube in number of components, | c | 19-0 |
| Block dimension register (0x10) | |||
| Block width | The width of each block minus one | t | 11-0 |
| Block height | The height of each block minus one | t | 23-12 |
| Depth | The depth of each block | c | 31-24 |
| Block skip register (0x14) | |||
| Block skip | Number of components to skip from first pixel in current block to first pixel in next block | c | 15-0 |
| Last block skip | Number of components to skip from first pixel in current block to first pixel in next block, when current block is the last block | c | 31-16 |
| Number of blocks register (0x18) | |||
| Blocks Y | Number of blocks in Y direction minus one | 8-0 | |
| Blocks X | Number of blocks in X direction minus one | 17-9 | |
| Offset register (0x1C) | |||
| Offset | Number of components to skip from start of HSI cube | c | 31-0 |
| S2MM (from AXI-Stream to memory) | |||
| Control register (0x20) | |||
Start | Core starts transfer when this bit is set to 1 | 0 | |
| Error IRQ enable | Trigger IRQ when error condition arises | 4 | |
| Completion IRQ enable | Trigger IRQ when transfer is complete | 5 | |
| Status register (0x24) | |||
| Transfer done | Indicates that transfer has completed | 0 | |
| Error code | Indicates error condition that occured during transfer | 3-1 | |
| Error IRQ flag | Read: 1 when IRQ triggered due to error Write: Writing 1 clears the IRQ flag | 8 | |
| Completion IRQ flag | Read: 1 when IRQ triggered due to completion Write: Writing 1 clears the IRQ flag | 9 | |
| Base address register (0x28) | |||
| Base address | Address of the first component in the HSI cube | b | 31-0 |